application note AN19 AN19-1 interfacing the x25650 to 8051 microcontrollers by applications staff, august 1994 the following code demonstrates how xicor's x25650 family of spi serial e 2 proms can be interfaced to the 8051 microcont r oller family when connected as shown in figure 1. the interface uses 4 lines from port 1, where cs is on p1.0, si on p1.1, sck on p1.2, and so on p1.3. additional code that will implement interfaces between the 8051 microcontroller family and other xicor serial devices can be found on the xicor web site at http://www.xicor.com. figure 1. typical hardware connection for interfacing an x25650 to 8051 microcontrollers x25650
xicor application note AN19-2 AN19 ;*********************************************************************************** ;* this code is designed to show how the xicor x25650 spi serial eeprom can ;* be interfaced with the 8051 microcontroller. the interface uses the 8051 general ;* purpose parallel port 1 and connects p1.0 to the chip select line (/cs), p1.1 to ;* the serial input data line (si), p1.2 to the serial clock line (sck) and p1.3 to ;* the serial output data line (so). ;* ;* the command routines provided demonstrate the protocol for all x25650 operations. ;* these are: ;* ;* 1. set write enable latch ;* 2. reset write enable latch ;* 3. write status register ;* 4. read status register ;* 5. single byte write ;* 6. single byte read ;* 7. page write ;* 8. sequential read ;* ;* the program writes 00h to the status register; reads the status register; writes ;* 11h to address 555h in byte mode; performs a single byte read from address 555h; ;* writes 22h, 33h, 44h to addresses 1f00h, 1f01h, 1f02h in page mode; and performs ;* a sequential read from addresses 1f00h, 1f01h, 1f02h. ;* ;*********************************************************************************** * cs bit p1.0 ; port 1 bit 0 used for chip select (/cs) si bit p1.1 ; port 1 bit 1 used for serial input (si) sck bit p1.2 ; port 1 bit 2 used for serial clock (sck) so bit p1.3 ; port 1 bit 3 used for serial output (so) wren_inst equ 06h ; write enable latch instruction (wren) wrdi_inst equ 04h ; write disable latch instruction (wrdi) wrsr_inst equ 01h ; write status register instruction (wrsr) rdsr_inst equ 05h ; read status register instruction (rdsr) write_inst equ 02h ; write memory instruction (write) read_inst equ 03h ; read memory instruction (read) byte_addr equ 0555h ; memory address for byte mode operations byte_data equ 11h ; data byte for byte write operation page_addr equ 1f00h ; memory address for page mode operations page_data1 equ 22h ; 1st data byte for page write operation page_data2 equ 33h ; 2nd data byte for page write operation page_data3 equ 44h ; 3rd data byte for page write operation status_reg equ 00h ; status register max_poll equ 99h ; maximum number of polls init_state equ 01h ; initialization value for control ports slic equ 030h ; address location of slic (rest of system code) ;************************************ ;* reset vector to beginning of code ;************************************ org 0000h ; reset vectors to this location ljmp begin
AN19-3 xicor application note AN19 ;******************************* ;* start of program execution ;******************************* org 0120h begin: mov sp, #60h ; initialize stack pointer clr ea ; disable interupts mov p1, #init_state ; init. control lines (cs high, sck/si/so low) lcall wren_cmd ; set write enable latch lcall wrsr_cmd ; write 00h to status register lcall wren_cmd ; set write enable latch lcall byte_write ; write 11h to address 555h (byte write) lcall byte_read ; read from address location 555h (byte read) lcall wren_cmd ; set write enable latch lcall page_write ; page write 22h/33h/44h to addresses 1f00/1/2h lcall sequ_read ; sequential read from addresses 1f00/1/2h jmp slic ;*************************** ;* 1. set write enable latch ;*************************** wren_cmd: clr sck ; bring sck low clr cs ; bring cs low mov a, #wren_inst lcall outbyt ; send wren instruction clr sck ; bring sck low setb cs ; bring cs high ret ;***************************** ;* 2. reset write enable latch ;***************************** wrdi_cmd: clr sck ; bring sck low clr cs ; bring cs low mov a,#wrdi_inst lcall outbyt ; send wrdi instruction clr sck ; bring sck low setb cs ; bring cs high ret ;************************** ;* 3. write status register ;************************** wrsr_cmd: clr sck ; bring sck low clr cs ; bring cs low mov a, #wrsr_inst lcall outbyt ; send wrsr instruction mov a, #status_reg lcall outbyt ; send status register byte clr sck ; bring sck low
xicor application note AN19-4 AN19 setb cs ; bring cs high lcall wip_poll ; poll for completion of write cycle ret ;************************* ;* 4. read status register ;************************* rdsr_cmd: clr sck ; bring sck low clr cs ; bring cs low mov a, #rdsr_inst lcall outbyt ; send rdsr instruction lcall inbyt ; read status register byte clr sck ; bring sck low setb cs ; bring cs high ret ;********************* ;* 5. single byte write ;********************* byte_write: mov dptr, #byte_addr ; set address of byte to be written clr sck ; bring sck low clr cs ; bring cs low mov a, #write_inst lcall outbyt ; send write instruction mov a, dph lcall outbyt ; send high order address byte mov a, dpl lcall outbyt ; send low order address byte mov a, #byte_data lcall outbyt ; send data byte clr sck ; bring sck low setb cs ; bring cs high lcall wip_poll ; poll for completion of write cycle ret ;******************** ;* 6. single byte read ;******************** byte_read: mov dptr, #byte_addr ; set address of byte to be read clr sck ; bring sck low clr cs ; bring cs low mov a, #read_inst lcall outbyt ; send read instruction mov a, dph lcall outbyt ; send high order address byte mov a, dpl lcall outbyt ; send low order address byte lcall inbyt ; read data byte clr sck ; bring sck low setb cs ; bring cs high
AN19-5 xicor application note AN19 ret ;*************** ;* 7. page write ;*************** page_write: mov dptr, #page_addr ; set address of 1st byte to be written clr sck ; bring sck low clr cs ; bring cs low mov a, #write_inst lcall outbyt ; send write instruction mov a, dph lcall outbyt ; send high order address byte mov a, dpl lcall outbyt ; send low order address byte mov a, #page_data1 lcall outbyt ; send 1st data byte mov a, #page_data2 lcall outbyt ; send 2nd data byte mov a, #page_data3 lcall outbyt ; send 3rd data byte clr sck ; bring sck low setb cs ; bring cs high lcall wip_poll ; poll for completion of write cycle ret ;******************** ;* 8. sequential read ;******************** sequ_read: mov dptr, #page_addr ; set address of 1st byte to be read clr sck ; bring sck low clr cs ; bring cs low mov a, #read_inst lcall outbyt ; send read instruction mov a, dph lcall outbyt ; send high order address byte mov a, dpl lcall outbyt ; send low order address byte lcall inbyt ; read 1st data byte lcall inbyt ; read 2nd data byte lcall inbyt ; read 3rd data byte clr sck ; bring sck low setb cs ; bring cs high ret ;***************** ;* wip polling ;***************** wip_poll: mov r1, #max_poll ; set maximum number of polls wip_poll1: lcall rdsr_cmd ; read status register jnb acc.0, wip_poll2 ; if wip bit '0' write cycle completed
xicor application note AN19-6 AN19 djnz r1, wip_poll1 ; if wip bit '1' continue polling wip_poll2: ret ;*************** ;* send a byte ;*************** outbyt: mov r0, #08 ; set bit counter to eight outbyt1: clr sck ; bring sck low rlc a ; shift byte left through carry mov si, c ; send data bit in carry setb sck ; bring sck high djnz r0, outbyt1 ; finish if last data bit clr si ; place si in known condition ret ;**************** ; recieve a byte ;**************** inbyt: mov r0, #08 ; set bit counter to eight inbyt1: clr sck ; bring sck low mov c, so ; receive data bit and store in carry rlc a ; shift byte left through carry setb sck ; bring sck high djnz r0, inbyt1 ; finish if last data bit ret
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